(China (Mainland))
Product Summary
The H5DU5162ETR-E3C is a 536,870,912-bit CMOS Double Data Rate (DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The H5DU5162ETR-E3C offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs of the H5DU5162ETR-E3C are latched on the rising edges of the CK (falling edges of the /CK) , Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
Parametrics
H5DU5162ETR-E3C absolute maximum ratings: (1) Operating Temperature (Ambient) TA: 0 to 70°C; (2) Storage Temperature TSTG: -55 to 150°C; (3) DD relative to VSS Voltage on VSS, VDD: -1.0 to 3.6V; (4) Voltage on VDDQ relative to VSS VDDQ: -1.0 to 3.6V; (5) Voltage on inputs relative to VSS, VINPUT: -.1.0V to 3.6V; (6) Voltage on I/O pins relative to VSS, VIO: -0.5 to 3.6V; (7) Output Short Circuit Current IOS: 50mA; (8) Soldering Temperature. Time, TSOLDER: 260°C, 10 sec.
Features
H5DU5162ETR-E3C features: (1) VDD, VDDQ=2.5V +/- 0.2V; (2) All inputs and outputs are compatible with SSTL_2 interface; (3) Fully differential clock inputs (CK, /CK) operation; (4) Double data rate interface; (5) Source synchronous - data transaction aligned to bidirectional data strobe (DQS) ; (6) On chip DLL align DQ and DQS transition with CK transistion; (7) DM mask write data-in at the both rising and falling edges of the data strobe; (8) All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (9) Programmable burst length 2/4/8 with both sequential and interleave mode; (10) Auto refresh and self refresh supported; (11) refresh cycles/64ms; (12) JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch.
Diagrams
